With the increasing complexity of integrated circuits and evolution to large scale integration (LSI), very large scale integration (VLSI), and very high-speed integrated circuits (VHSIC) testability issues have become of paramount importance. Whereas in the past integrated circuits were relatively small and contained only simple structures, today's most advanced integrated circuits are extremely complex and contain hundreds of thousands of circuit elements. The simplicity of the early integrated circuits made testing simple and if the integrated circuit failed a test, it was cost effective to simply throw out the bad chip. Further, testing of such simple integrated circuits is straight forward because there are few, if any, inaccessible circuits on the chip and chip simplicity allows quick and thorough testing.
With the advent of LSI, VLSI, and VHSIC chips, direct accessibility to individual circuits on the chip is greatly limited. This is due to the vastly increased number of circuits on the chip and to the microscopic dimensions of these circuits. Testing these circuits is a major concern in today's electronics industry. The problem of testing LSI, VLSI, and VHSIC chips is further aggravated by the presence of inaccessible storage elements or latches that are typically embedded among combinatorial logic networks. Without an assured technique for setting and examining the logic states of these embedded latches, there can be no effective testing of the associated combinatorial logic networks. Yet reliable and thorough testing of all LSI, VLSI, and VHSIC chips is indispensable in manufacturing as well as maintenance.
Two popular techniques for testing today's integrated circuits are functional tests and structural tests. Functional testing uses the normal circuit behavior to test the integrated circuit. In functional testing, the integrated circuit is operated to output a sequence of test data based on an appropriate input sequence of test data. Comparing the desired output test data with the test results from the chip provides a determination of the condition of the chip. The various input test data can be applied to the chip for testing various logic blocks of the chip. From a system's level viewpoint, functional testing can be accomplished during normal chip operation or during a designated test sequence.
It is obvious, however, that as the number of logic circuits on the chip increases many of the logic circuits cannot be adequately tested with the functional scheme. Although functional testing is currently the most popular test technique, it also provides the lowest degree of test effectiveness in detecting all possible "stuck at" faults and requires the highest level of customization, i.e., designing the chip to accommodate the testing features. Functional testing requires isolation of the chip under test and the test data must simulate the circuitry to which the chip would normally be connected. Thus, in addition to incomplete controllability and accessibility, there are also more places for the test circuitry itself to fail, thus giving a false error detection or inhibiting the reporting of a real operational fault. Functional circuit testing also requires the test circuitry to be customized to match the architecture and functions of the chip under test and ironically, may require as much or more effort to design than the chip to be tested.
Structural testing involves the use of on-chip circuitry dedicated to chip testing. The structural technique does not require an understanding of the function of each integrated circuit block, and therefore can be developed in a generic way to be applicable to a large class of LSI, VLSI, or VHSIC chips. The most popular structural test technique is the scan-in/scan-out (or level sensitive scan design, LSSD) methodology. With this system, in the test mode all the latches in a circuit are arranged into a string of shift registers and test data is clocked through the string to test for bad latches. Test data is then loaded into the combinatorial logic in parallel and shifted out in series to check the combinatorial logic that connects the latches together.